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  1. #1
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    Default Investigacion Pitufa


    Muy buenas a[email protected], dejo esto aqui por si alguno quiere animarse e ir soltando prenda, tal vez sea interesante centrarnos un poco en el estudio de esta, ya que en principio parece que no cambia.

    Comento, tengo una deseando desvelarme su secreto, solo necesito un programilla capaz de hacer dump. "Poca cosa verdad"

    Se rumorea que existe y no lo sueltan, si alguno os enterais de algo, pues eso, a ver si por ahi podemos entrar.

    Saludos
    Antena mirando pa´chispa
    Dreambox 500s del pais de Mao
    Tompsom con blanquita y pagando tos los meses

    El saber no ocupa lugar, pero ocupa mucho tiempo.

    Y librame Diós de mis amigos, que de mis enemigos ya me libraré yo.

  2. #2
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    Default

    bueno podemos empezar posteando el tipo de chip que trae la V9 que seria el ST19XL34, mejor tener este dato por si lo necesitamos.
    Flores? seguro que se me adelantan a postearlas
    Noticias? si están en internet las encontraré.
    Rumores? si se rumorea algo seguro que lo sabré.


  3. #3
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    Default

    el amigo formiche ha encontrado firm que emulan la pitufa, asi que parece que estos años de investigacion estan saliendo a la luz, y en pocas semanas estara todo abierto, si se confirman estos firm.
    Last edited by costalero69; 30th November 2007 at 18:38.
    Flores? seguro que se me adelantan a postearlas
    Noticias? si están en internet las encontraré.
    Rumores? si se rumorea algo seguro que lo sabré.


  4. #4
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    Default Estudio Sacado De Zackyfiles

    EMM - SECA

    C1 40 01 00 67 40 04 65 41 01 82 00 18 94 91 8e 10 D7 92 40 F8 3f 35 E5 0e Cf Be 62 A4 E7 82 39 84 82 73 F3 D0 78 13 79 D8 03 58 7c D9 Fd 6e 88 Cd 5c C7 54 F9 58 C7 2a 15 9d Cb 8a 24 E7 34 42 75 D3 7f E6 A7 1c 19 21 4d 97 F1 15 56 7c 6f 25 E4 E8 F6 6f Cc Ba 3e 6d 53 2d 4b 2b 1e 5e 48 30 B9 D5 Dc 76 9c 68 02 F5 91 8a 00 F0 0c

    Como Va Encriptada Con La Parity***2 La Cual Es Igual Para Todas Las Tarjetas Pitufas, Pues Le Quito La Cabecera Seca, Le Pongo Una Cabecera Nagra Y Me Queda AsÍ:

    00406da0ca000067 04 65 41 01 82 00 18 94 91 8e 10 D7 92 40 F8 3f 35 E5 0e Cf Be 62 A4 E7 82 39 84 82 73 F3 D0 78 13 79 D8 03 58 7c D9 Fd 6e 88 Cd 5c C7 54 F9 58 C7 2a 15 9d Cb 8a 24 E7 34 42 75 D3 7f E6 A7 1c 19 21 4d 97 F1 15 56 7c 6f 25 E4 E8 F6 6f Cc Ba 3e 6d 53 2d 4b 2b 1e 5e 48 30 B9 D5 Dc 76 9c 68 02 F5 91 8a 00 F0 0c

    Voy Al Programa Ese Nuevo Del Upload, El Nagradecrypter, Le Intruduzco Como Emm Y Que Es Lo Que Me Da?

    Me Da Esto:
    7f9c15977e82e47f410112be3c1a12c600002003033309b473 12b0000012 C6a8be12c6a8bfe017210309e0e317f818001fd600026212c6 00006312c6 00000000000000000000000000000000000000000000000000 0000000000 000000000000

    7f9c15977e82e47f
    4101
    12be3c1a
    12c60000
    2003033309b473
    12b00000
    12c6a8be
    12c6a8bf
    E017210309e0e317f818001fd6000262
    12c60000
    6312c6
    00
    00000000000000000000000000000000000000000000000000 0000000000 0000000000

    Esto Es La Monda . Si Yo Fuera Polanco Les Fusilaba A Todos
    Flores? seguro que se me adelantan a postearlas
    Noticias? si están en internet las encontraré.
    Rumores? si se rumorea algo seguro que lo sabré.


  5. #5
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    Default

    Hola costalero, ¿ A que programa nuevo te refieres ?

    No, no lo pillo ese decifrado, por mas vueltas que le doy, lo unico que veo claro que es una instr. al 4101, pero no se, la verdad estoy un poco liado sacandole humo a la pitufa, que estaba llena de polvo, je je

    Saludos
    Antena mirando pa´chispa
    Dreambox 500s del pais de Mao
    Tompsom con blanquita y pagando tos los meses

    El saber no ocupa lugar, pero ocupa mucho tiempo.

    Y librame Diós de mis amigos, que de mis enemigos ya me libraré yo.

  6. #6
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    Default

    Quote Originally Posted by ivanosky View Post
    Hola costalero, ¿ A que programa nuevo te refieres ?

    No, no lo pillo ese decifrado, por mas vueltas que le doy, lo unico que veo claro que es una instr. al 4101, pero no se, la verdad estoy un poco liado sacandole humo a la pitufa, que estaba llena de polvo, je je

    Saludos

    jajjaa, a ver compañero, si lees un poco en off topy parece ser que formiche ha encontrado unos firm que trabajan en seca 3 con auto, y parece que el tio max esta tarde ha sacado tambien firm para seca 3, si se confirma, el apagon duraria solo unas semanas el tiempo de sacar firm en seca3, en cuanto al descifrado, si lo miras atentamente solo cambia la cabecera le quitas la cabecera de seca y se la cambias por una de nagra y es una emm de nagra, solo cambia la cabecera, por lo que es una autentica chapuza lo que hacen los de pigi, son emm de nagra con cabeceras de seca.
    Flores? seguro que se me adelantan a postearlas
    Noticias? si están en internet las encontraré.
    Rumores? si se rumorea algo seguro que lo sabré.


  7. #7
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    Default

    Joder, ya lo decia yo por eso no encontraba sentido, con el cacao mental que tengo, jajajaja

    No hagais caso de los bulos o fakes, se ve de todo, desde el listillo que lo ve todo, hasta el que me parece mas serio que dice que de eso nada.

    Me refiero al famoso firm de hoy, yo lo he abierto y no se parece mucho a los que conozco.

    Saludos
    Antena mirando pa´chispa
    Dreambox 500s del pais de Mao
    Tompsom con blanquita y pagando tos los meses

    El saber no ocupa lugar, pero ocupa mucho tiempo.

    Y librame Diós de mis amigos, que de mis enemigos ya me libraré yo.

  8. #8
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    Default

    No se si se será util, la verdad es que no tengo mucha idea de esto, peró hago lo que puedo:

    http://share.gooddvdstuff.com/1206795

    http://share.gooddvdstuff.com/6816748

    "Busca tu PPUA en SECA_HTML y envia su correspondiente INS con el programa Moscazul.
    Descarga Moscazul y fichero SECA_HTML AQUI:
    http://rapidshare.com/files/73789982/FechaseKa3.rar
    "
    Es todo en buena fe, repito, no me entero mucho pero uno de ustedes le puede dar un vistazo...
    Saludos
    PS: no se si puedo escribir la url, es que no sabia como subir los archivos...

  9. #9
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    Default Para Bluek

    Gracias amigo por tu aportacion, tiene muy buena pinta.

    Contiene actualizaciones con rango PPUA, gracias a ellas he actualizado la fecha en mi pitufa a Enero 2008.

    Tiene un enlace muy bueno a una pag. de actualizaciones.

    Y eso buscando buscando, a ver si encontramos la manera de reventarla.

    Gracias de nuevo, entre todos lo conseguiremos.

    Un saludo
    Antena mirando pa´chispa
    Dreambox 500s del pais de Mao
    Tompsom con blanquita y pagando tos los meses

    El saber no ocupa lugar, pero ocupa mucho tiempo.

    Y librame Diós de mis amigos, que de mis enemigos ya me libraré yo.

  10. #10
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    Default

    Aqui pongo para su estudio, un desensamblado de una emm de actualizacion de fecha.


    C1 40 41 00 67 04 65 41 01 81 00 98 10 BB 29 A6 B0 B2 1C AD 66 71 3D FF 2F 4F 68 DB 9E E5 4B 13 80 81 C6 03 77 EA 01 1F BC 1F BD 1D C8 B7 14 4E A6 97 DB 17 3F 1B 25 97 DF 39 DB 60 DF 90 87 2A F7 02 F3 F1 A3 F1 1C 0A 84 C1 F0 EC B4 08 6A AD 04 24 63 12 6B 86 93 39 96 65 CB AB 5A 27 24 8A 01 E3 8A DE 8F 89 5A 37 4B FB 50 62


    Desens.

    $000000: C14041 CP A,($4041) ; Compara el byte de la direccion $4041 con A
    $000003: 006704 BTJT ($67),#00,$000A ; Si el bit 00 del byte en $67 vale 1 salta a $000A
    $000006: 65 db.b 65
    $000007: 41 db.b 41
    $000008: 018100 BTJF ($81),#00,$000B ; Si el bit 00 del byte en $81 vale 0 salta a $000B
    $00000B: 98 RCF ; Desactiva el bit C
    $00000C: 10BB BSET ($BB),#00 ; Activa el bit 00 del byte en $BB
    $00000E: 29A6 JRH $FFB6 ; Si H = 1 salta a $FFB6
    $000010: B0B2 SUB A,($B2) ; Resta el byte de la direccion $B2 de A
    $000012: 1CAD BSET ($AD),#06 ; Activa el bit 06 del byte en $AD
    $000014: 6671 RRC ($71,X) ; Rota un bit hacia la derecha el byte que hay en ($71+X)
    $000016: 3DFF TNZ ($FF) ; Comprueba si el byte que esta en $FF es negativo o Cero
    $000018: 2F4F JRIH $0069 ; Si la linea de Intrrrupcion es alta salta a $0069
    $00001A: 68DB SLL ($DB,X) ; Desplaza un bit a la izquierda el byte que hay en ($DB+X)
    $00001C: 9E LD A,S ; Guarda en A el valor del stack
    $00001D: E54B BCP A,(RC2.LSb,X) ; Comparacion de Bit del byte de la direccion (RC2.LSb+X) con A
    $00001F: 1380 BRES ($80),#01 ; Desactiva el bit 01 del byte en $80
    $000021: 81 RET ; Vuelve de una Subrutina
    $000022: C60377 LD A,($0377) ; Carga en A el valor del byte de la direccion $0377
    $000025: EA01 OR A,($01,X) ; Hace el OR del byte de la direccion ($01+X) con A
    $000027: 1FBC BRES ($BC),#07 ; Desactiva el bit 07 del byte en $BC
    $000029: 1FBD BRES ($BD),#07 ; Desactiva el bit 07 del byte en $BD
    $00002B: 1DC8 BRES ($C,#06 ; Desactiva el bit 06 del byte en $C8
    $00002D: B714 LD ($14),A ; Guarda el valor de A en la direccion $14
    $00002F: 4E SWAP A ; Da la vuelta a los nibbles de A
    $000030: A697 LD A,#97 ; Carga en A el valor 97
    $000032: DB173F ADD A,($173F,X) ; Suma el byte de la direccion ($173F+X) con A
    $000035: 1B25 BRES ($25),#05 ; Desactiva el bit 05 del byte en $25
    $000037: 97 LD X,A ; Guarda en X el valor de A
    $000038: DF39DB LD ($39DB,X),X ; Guarda el valor de X en la direccion ($39DB+X)
    $00003B: 60DF NEG ($DF,X) ; Complemento a 2 del byte que hay en ($DF+X)
    $00003D: 90 db.b 90
    $00003E: 87 ERET ; Vuelve de una Subrutina
    $00003F: 2AF7 JRPL $0038 ; Si N = 0 salta a $0038
    $000041: 02F3F1 BTJT ($F3),#01,$0035 ; Si el bit 01 del byte en $F3 vale 1 salta a $0035
    $000044: A3F1 CP X,#F1 ; Compara F1 con X
    $000046: 1C0A BSET ($0A),#06 ; Activa el bit 06 del byte en $0A
    $000048: 84 POP A ; Recupera un byte del stack y lo pone en A
    $000049: C1F0EC CP A,($F0EC) ; Compara el byte de la direccion $F0EC con A
    $00004C: B408 AND A,(COUNT_TIMER0) ; Hace el AND del byte de la direccion COUNT_TIMER0 con A
    $00004E: 6AAD DEC ($AD,X) ; Resta 1 al byte que hay en ($AD+X)
    $000050: 042463 BTJT ($24),#02,$00B6 ; Si el bit 02 del byte en $24 vale 1 salta a $00B6
    $000053: 126B BSET ($6B),#01 ; Activa el bit 01 del byte en $6B
    $000055: 86 POP CC ; Recupera un byte del stack y lo pone en CC
    $000056: 93 LD X,Y ; Guarda en X el valor de Y
    $000057: 3996 RLC ($96) ; Rota un bit hacia la izquierda el byte que esta en $96
    $000059: 65 db.b 65
    $00005A: CBAB5A ADD A,($AB5A) ; Suma el byte de la direccion $AB5A con A
    $00005D: 2724 JREQ $0083 ; Si Z = 1 salta a $0083
    $00005F: 8A PUSH CC ; Pone el valor de CC en el Stack
    $000060: 01E38A BTJF ($E3),#00,$FFED ; Si el bit 00 del byte en $E3 vale 0 salta a $FFED
    $000063: DE8F89 LD X,($8F89,X) ; Carga en X el valor del byte de la direccion ($8F89+X)
    $000066: 5A DEC X ; Resta 1 a X
    $000067: 374B SRA (RC2.LSb) ; Desplaza hacia la derecha los bits del byte que esta en RC2.LSb menos el 7
    $000069: FB ADD A,(X) ; Suma el byte de la direccion que hay en X con A
    $00006A: 50 NEG X ; Complemento a 2 del registro X (cambiar de signo)
    $00006B: 62 db.b 62

    Saludos
    Last edited by ivanosky; 3rd December 2007 at 12:58.
    Antena mirando pa´chispa
    Dreambox 500s del pais de Mao
    Tompsom con blanquita y pagando tos los meses

    El saber no ocupa lugar, pero ocupa mucho tiempo.

    Y librame Diós de mis amigos, que de mis enemigos ya me libraré yo.

  11. #11
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    vamos a ver si lo pillo.
    yo he programado automatas, algebra de boole, asi como diagramas de contactos, etc.
    por lo que veo, si se conoce las direcciones de memoria, se pueden rotar bits, sumar etc?, es correcto no?.
    aqui hablamos en hexadecimal, pero tambien podemos hacerlo en binario.
    y hacer palabras(words), asi como dobles palabras, y agruparlas no?
    hasta hay, lo tengo claro.
    tenemos la rom y la ram, en la rom tenemos las direcciones y la informacion, que no podemos modificar, y la ram seria la que modificariamos, con las instrucciones, que nos envian, no?.

    a ver si pillo la onda.

  12. #12
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    Default

    Das123 hasta ahi vas bien, pero tu que parece que sabes, estrujate un pelin mas el cerebro, ademas de ROM y RAM el st 19 xl 34 que bien apunto mas arriba el amigo costalero69, tambien lleva 34 Kb de memoria EEprom.

    La cuestion es como acceder a ella, que es la que nos interesa ya que como sabes la RAM no nos sirve de nada, en cuanto se queda sin alimentacion, off off off.

    Un saludo
    Antena mirando pa´chispa
    Dreambox 500s del pais de Mao
    Tompsom con blanquita y pagando tos los meses

    El saber no ocupa lugar, pero ocupa mucho tiempo.

    Y librame Diós de mis amigos, que de mis enemigos ya me libraré yo.

  13. #13
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    Default

    Electrically Erasable Programmable Read only Memory, eeprom, si no recuerdo mal, es una memoria no volatil, para almacenar datos.
    en el automata de simens st-200, con la cpu 214 direccionv-0 a v-511,
    se leia, justo al iniciar el automata el programa.
    ya se que te sonara a chorrada, pero la eeprom, se volcaba, junto con el programa para meter al plc .

    hasta hay creo que no hemos tropezado no?

    Saludos

    http://www.datasheetcatalog.com/data...ST19XL34.shtml.

    Pd, ya veo, el problema no es leer solo la eprom, lo que me tengo que mirar es la ISO 7816, hay vendra especificado la velocidad/lectura etc no?
    Last edited by das123; 4th December 2007 at 08:23.

  14. #14
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    esquema segun iso del micro de marras, segun iso y mas datos creo, que alguien lo corrija si no es asi, ojo al ladrillo.



    Part 3: Electronic Signals and Transmission Protocols ISO 7816 [Part 1] [Part 2] [Part 3] [Part4]
    This part describes electronic signals and transmission protocols of integrated circuit cards. We copied it from a version that is available on the Internet. If you need the official version of this part, please contact ISO in Switzerland. If you have suggestions or material to include (tables, graphs etc) please contact us. The document will stay at this location for anyone that wants a direct link to this part of the standard. We will edit this document as necessary to bring it up to date and add comments.
    Most of ISO7816-3 is important for reader manufacturers or developers who want to establish a communication with a smart card on a very low level (the signal level). Going through ISO 7816-3 you will see what's involved in writing your own I/O software. This can be either to communicate from a microcontroller or a PC's serial/parallel/USB/PCMCIA port. Even if you don't go that far, it is interesting to read about what you can get out of an Answer to Reset (ATR).
    There are many tools out there to read an ATR. Even on this site we put a remote version of a free ATR probing tool that reads and interprets an ATR over the Internet. All you need is a PCSC compliant smart card reader attached to a PC with an Internet connection.
    Electrical Signals Description

    I/O : Input or Output for serial data to the integrated circuit inside the card.
    VPP : Programing voltage input (optional use by the card).
    GND : Ground (reference voltage).
    CLK : Clocking or timing signal (optional use by the card).
    RST : Either used itself (reset signal supplied from the interface device) or in combination with an interal reset control circuit (optional use by the card). If internal reset is implemented, the voltage
    supply on Vcc is mandatory.
    VCC : Power supply input (optional use by the card).

    NOTE - The use of the two remaining contacts will be defined in the appropriate application standards.

    ISO7816 3.1 Voltage and current values

    Abbreviations:
    Vih : High level input voltage
    Vil : Low level input voltage
    Vcc : Power supply voltage at VCC
    Vpp : Programming voltage at VPP
    Voh : High level output voltage
    Vol : Low level output voltage
    tr : Rise time between 10% and 90% of signal amplitude
    tf : Fall time between 90% and 10% of signal amplitude
    Iih : High level input current
    Iil : Low level input current
    Icc : Supply current at VCC
    Ipp : Programming current at VPP
    Ioh : High level output current
    Iol : Low level output current
    Cin : Input capacitance
    Cout: Output capacitance

    * I/O
    This contact is used as input (reception mode) or output (transmission mode) for data exchange. Two possible states exist for I/O:
    - mark or high state (State Z), if the card and the interface device are in reception mode or if the state is imposed by the transmitter.

    - space or low state (State A), if this state is imposed by the
    transmitter.
    When the two ends of the line are in reception mode, the line shall be maintained in state Z. When the two ends are in non-matced transmit mode, the logic state of the line may be indeterminate. During operations, the interface device and the card shall not both be in transmit mode.

    Table 1 - Electrical characteristics of I/O under normal operation conditions.
    ,--------+--------------------------------+---------+---------+------,| Symbol | Conditions | Minimum | Maximum | Unit |+--------+--------+-----------------------+---------+---------+------+| | Either | Iih max = +/- 500uA | 2 | VCC | V || Vih | (1) +-----------------------+---------+---------+------+| | or | Iih max = +/- 50uA | 0.7 VCC | VCC (3) | V |+--------+--------+-----------------------+---------+---------+------+| Vil | Iil max = 1mA | 0 | 0.8 | V |+--------+--------------------------------+---------+---------+------+| | Either | Iol max = +/- 100uA | 2.4 | VCC | V || Voh | +-----------------------+---------+---------+------+| (2) | or | Iol max = +/- 20uA | 3.8 | VCC | V |+--------+--------+-----------------------+---------+---------+------+| Vol | Iol max = 1mA | 0 | 0.4 | V |+--------+--------------------------------+---------+---------+------+| tr, tf | Cin = 30pF; Cout = 30pF | | 1 | us |+--------+--------------------------------+---------+---------+------+| (1) For the interface device, take into account both conditions. || (2) It is assumed that a pull up resistor is used in the interface || device (recommended value 20k Ohm. || (3) The voltage on I/O shall remain between 0.3V and VCC+0.3V. |'--------------------------------------------------------------------'
    * VPP
    This contact may be to supply the voltage required to program or to erase the internal non-volatile memory. Two possible states exists for VPP: Idle state and active state, as defined in table 2. The idle state shall be maintained by the interface device unless the active state is required.

    Table 2 : Electrical characteristics of VPP under normal operation conditions.
    ,--------+--------------------------------+---------+---------+------,| Symbol | Conditions | Minimum | Maximum | Unit |+--------+--------------------------------+---------+---------+------+| Vpp | Idle State | 0.95*Vcc| 1.05*Vcc| V || Ipp | (programming non active) | | 20 | mA |+--------+--------------------------------+---------+---------+------+| Vpp | Active State | 0.975*P | 1.025*P | V || Ipp | (programming the card) | | I | mA |+--------+--------------------------------+---------+---------+------+| The card provides the interface with the values of P and I || (default values: P=5 and I=50) |'--------------------------------------------------------------------'Rise of fall time : 200 us maximum. The rate of change of Vpp shall not exceed 2V/us.
    The maximum power Vpp*Ipp shall not exceed 1.5W when averaged over any period of 1s.

    * CLK
    The actual frequency, delivered by the interface device on CLK, is designated either by fi the initial frequency during the answer to reset, or by fs the subsequent frequency during subsequent transmission.
    Duty cycle for asynchronous operations shall be between 45% and 55% of the period during stable operation. Care shall be taken when switching frequencies (from fi to fs) to ensure that no pulse is shorter than 45% of the shorter period.

    Table 3 - Electrical characteristics of CLK under normal operation conditions.
    ,--------+--------------------------------+---------+---------+------, | Symbol | Conditions | Minimum | Maximum | Unit | +--------+--------+-----------------------+---------+---------+------+ | | Either | Iih max = +/- 200uA | 2.4 | VCC (2) | V | | | (1) +-----------------------+---------+---------+------+ | Vih | or | Iih max = +/- 20uA | 0.7*VCC | VCC (2) | V | | | (1) +-----------------------+---------+---------+------+ | | or | Iih max = +/- 10uA | VCC-0.7 | VCC (2) | V | +--------+--------+-----------------------+---------+---------+------+ | Vil | Iil max = +/-200 uA | 0 (2) | 0.5 | V | +--------+--------------------------------+---------+---------+------+ | tr, tf | Cin = 30pF | |9% of the period| | | | |with a max:0.5us| +--------+--------------------------------+---------+---------+------+ | (1) For the interface device, take into account three conditions. | | (2) The voltage on CLK shall remain between 0.3V and Vcc+0.3V. | '--------------------------------------------------------------------'* RST Table 4 - Electrical characteristics of RST under normal operation conditions.
    ,--------+--------------------------------+---------+---------+------, | Symbol | Conditions | Minimum | Maximum | Unit | +--------+--------+-----------------------+---------+---------+------+ | | Either | Iih max = +/- 200uA | 4 | VCC (2) | V | | Vih | (1) +-----------------------+---------+---------+------+ | | or | Iih max = +/- 10uA | VCC-0.7 | VCC (2) | V | +--------+--------+-----------------------+---------+---------+------+ | Vil | Iil max = +/- 200uA | 0 (2) | 0.6 | V | +--------+--------------------------------+---------+---------+------+ | (1) For the interface device, take into account both conditions. | | (2) The voltage on RST shall remain between 0.3V and VCC+0.3V. | '--------------------------------------------------------------------'* VCC This contact is used to supply the power voltage Vcc.

    Table 5 - Electrical characteristics of VCC under normal operation conditions.
    ,--------+---------+---------+-------, | Symbol | Minimum | Maximum | Unit | +--------+---------+---------+-------+ | Vcc | 4.75 | 5.25 | V | | Icc | | 200 | mA | '--------+---------+---------+-------'ISO7816 3.2 Operating procedure for integrated circuit(s) cards

    This operating procedure applies to every integrated circuit(s) card with contacts:
    The dialogue between the interface device and the the card shall be conducted through the consecutive operations:
    - connection and activation of the contacts by the interface device.
    - reset of the card.
    - answer to reset by the card.
    - subsequent information exchange between the card and the interface device.
    - desactivation of the contacts by the interface device.
    These operations are specified in the following subclauses.
    NOTE :
    An active state on VPP should not only be provided and maintained when requested by the card.
    ISO7816 3.2.a - Connection and activation of the contacts

    The electrical circuits shall not be activated until the contacts are connected to the interface device so as to avoid possible damage to any card meeting these standards.
    The activation of the contacts by the interface device shall consist of the consecutive operations:
    - RST is in state L;
    - VCC shall be powered;
    - I/O in the interface device shall be put in reception mode;
    - VPP shall be raised to idle state;
    - CLK shallbe provided with a suitable and stable clock.

    ISO7816 3.2.b - Reset of the card

    A card reset is initiated by the interface device, whereupon the card shall respond with an Answer to Reset as describe in 2.4.
    By the end of the activation of the contacts (RST is in L, VCC powered and stable, I/O in reception mode in the interface device, VPP stable at idle level, CLK provided with a suitable and stable clock), the card answering asynchronously is ready for reset.
    The clock signal is applied to CLK at time T0. The I/O line shall be set to state Z within 200 clcok cycles of the clock signal (t2) being applied to CLK (time t2 after T0).
    An internally reset card reset after a few cycles of clock signal. The Answer to Reset on I/O shall begin between 400 and 40 000 clock cycles (t1) after the clock signal is applied to CLK (time t1 after T0).
    A card with an active low reset is reset by maintaining RST in state L for at least 40 000 clock cycles (t3) after the clock signal is applied on CLK (time t3 after T0). Thus if no Answer to Reset begind within 40 000 clock cycles (t3) with RST in state L, RST is put to state H (at time T1). The
    Answer to Reset on I/O shall begin between 400 and 40 000 clock cycles (t1) after the rising edge of the signal on RST (time t1 after T1).
    If the Anwser to Reset does not begin within 40 000 clock cycles (t3) with RST in state H (t3 after T1), the signal on RST shall be returned to state L (at time T2) and the contacts shall be desactivated by the interface device.
    GND __________________________________________________ ______________________ __________________________________________________ ________________VCC _| : ___ :_________________________________________________ ______________:VPP __|: |____ : t3 t3 : :<--------------------------->:<------------------------------->: : :_________________________________:RST ___:_____________________________| |____ : : :CLK ___||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||____ : t1 : : :<-------------->: : : : __________:____________:__________________________ _______:I/O __XXXXXXXX |____________:_______Answer____________________:XX XX(IR) : : : : : t2 : : t1 : :<---->: :<---------->: : : _______________________:__________________________ _______:I/O __XXXXXXXX : |______Answer________:XXXX(AL) : t2 : : : :<---->: : : : :_________________________________:I/O __XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX: :XXXXX(SH) : : : T0 T1 T2 IR : Internal Reset t2 <= 200/fi AL : Asynchronous Reset 400/fi <= t1 <= 40000/fi SH : Syncronous Reset 40000/fi <= t3 Figure1 : Reset of the card With a card answering synchonously, the interface device sets all the lines to state L (See figure 2). VCC is the powered, VPP is set to idle state, CLK and RST remain in L state, I/O is put in reception mode in the interface device, RST shall be maintained in state H for at least 50 us (t12), before returning to state L again.
    The clock pulse is applied after an interval (t10) from the rising edge of the reset signal. The duration of the state H of the clock pulse can be any value between 10 us and 50 us ; no more than one clock pulse during reset high is allowed. The time interval between the falling edges on CLK
    and RST is t11.
    The first data bit is obtained as an answer to reset on I/O while CLK is in state L and is valid after an interval t13 from the falling edge on RST.
    __________________________________________________ ____________________VCC__/ __________________________________________________ ___________________VPP___/ t12 :<---------------->: :__________________:RST_____/: \_______________________________________________ : : : t10 t11 : t15 t16 :<---->: :<---->: t14 :<---->: :<---->: : ____ : :<---->: :______: : : _______CLK_____________:/ 1 \:______:______:/ 2 \:______:/ 3 \_______ : : : t13 : t17 :<---->: :<---->: _____________________________ :______________ :______________ ___I/O___//////////////////////////////\:_______1______X-X_______2_______X-X___5us <= t10 10us <= t14 <= 100us Clock low after RST5us <= t11 10us <= t15 <= 50us Clock High50us <= t12 ........ Reset High 10us <= t16 <= 100us Clock Lowt13 <= 10us Propagation delay t17 <= 10us Propagation delay Figure2 : Reset of the card when a synchronous answer is expected.
    NOTES:
    1 - The internal state of the card is assumed not to be defined before reset. Therefore the design of the card has to avoid inproper operation.
    2 - In order to continue the dialogue with the card, RST shall be maintained in the state where an answer occurs on I/O.
    3 - Reset of a card can be initiated by the interface device at its discetion at any time.
    4 - Interface devices may support one or more of these types of reset behaviour. The priority of testing for asynchronous or synchronous cards is not defined in this standard.

    ISO7816 3.2.c - Deactivation of the contacts

    When informations exchange is terminated or aborted (unresponsive card or detection of card removal), the electrical contacts shall be desactivated.
    The deactivation by the interface device shall consist of the consecutive operations:
    - State L on RST;
    - State L on CLK;
    - Vpp inactive;
    - State A on I/O;
    - VCC inactive;
    ISO7816 3.3 Answer to Reset

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    Part 3: Electronic Signals and Transmission Protocols ISO7816 3.3 Answer to Reset

    Two types of transmissions are considered:
    * Asynchronous transmission:
    In this type of transmission, characters are transmitted on the I/O line in an asynchronous half duplex mode. Each character includes an 8bit byte.

    * Synchronous transmission:
    In this type of transmission, a series of bits is transmitted on the I/O line in half duplex mode in synchronisation with the clock signal on CLK.
    ISO7816 3.1.a - Answer to Reset in asynchronous transmission

    * Bit duration
    """"""""""""
    The nominal bit duration used on I/O is defined as one Elementary Time Unit (etu).
    For cards having internal clock, the initial etu is 1/9600 s.
    For cards using the external clock, there is a linear relationship between the Elementary Time Unit used on I/O and the period provided by the interface device on CLK.
    The initial etu is 372/fi s where fi is in Hertz.
    The initial frequency fi is provided by the interface device on CLK during the Answer to Reset.
    In order to read the initial character (TS), all cards shall initially be operated with fi in the range of 1 MHz to 5 MHz.
    * Character frame during answer to reset
    """"""""""""""""""""""""""""""""""""""
    Prior to the transmission of a character, I/O shall be in state Z.
    A character consists of ten consecutive bits:
    - a start bit in state A;
    - eight bits of information, designated ba to bh and conveying a data byte;
    - a tenth bit bi used for even parity checking.
    A data byte consists of 8 bits designated b1 to b8, from the least significant bit (lsb, b1) to the most significant bit (msb, b.
    Conventions (level coding, connecting levels Z/A to digits 1 or 0: and a bit significance, connecting ba...bh to b1...b are specified in the initial character, call TS, which is transmitted by the card in response to reset.
    Parity is correct when the number of ONES is even in the sequence from ba to bi.
    Whithin a character, the time from the leading edge of the start bit to the trailing edge of the nth bit shall equal (n+/-0.2) etu.
    When searching for a start, the receiver samples I/O periodically. The time origin being the mean between last observation of level Z and first observation of level A, the start shall be verified before 0.7 etu, and then ba is received at (1.5 +/-0.2) etu. Parity is checked on the fly.
    NOTE : When searching for a start, the sampling time shall be less than 0.2 etu so that all the test zones are distinct from the transition zones.
    The delay between two consecutives characters (between start leading edges) is at least 12 etu, including a character duration (10+/-0.2) etu plus a guardtime, the interface device and the card reamain both in reception, so that I/O is in state Z.
    Start Parity Next bit <----- 8 data bits -----> bit Start bit Z ____ ________________________________......______ __ | | | | | | | | | | | | | I/O | |ba|bb|bc|bd|be|bf|bg|bh|bi| Guardtime | | |___|__|__|__|__|__|__|__|__|__| |___|_ A : : : : 0 t1 : t10 : : :<---- (n+/-0.2) etu --->: Figure 3: Character frame During the Answer to Reset, the delay between the start leading edges of two consecutives characters from the card shall not exeed 9600 etu. This maximum is named initial waiting time.
    * Error detection and character repetition
    """"""""""""""""""""""""""""""""""""""""
    During the answer to reset, the following characters repetition procedure depends on the protocol type. This procedure is mandatory for cards using the protocol type T=0; it is optional for the interface device and for the other cards.
    The transmitter tests I/O (11+/-0.2) etu after the start leading edge:
    - If I/O is in state Z, the correct reception is assumed.
    - If I/O is in state A, the transmission is assumed to have been incorrect. The disputed character shall be repeated after a delay of at least 2 etu after detection of the error signal.
    When parity is incorrect, from (10.5+/-0.2) etu, the receiver transmits an error signal at state A for 1 etu minimum and 2 etu maximum. The receiver then shall expect a repetition of the disputed character (see figure .
    If no character repetition is provided by the card, - The card ignores and shall not suffer damage from the error signal coming from the interface device.
    - The interface device shall be able to initiate the reception and the whole Answer to Reset response sequence.
    * Structures and content
    """"""""""""""""""""""
    A reset operation results in the answer from the card consisting of the initial character TS followed by at most 32 characters in the following order:
    - T0 ................... Format character (Mandatory) - TAi, TBi, TCi, TDi ... Interface characters (Optional) - T1, T2, ... ,TK ...... Historical characters (Optional) - TCK .................. Check character (Conditional)Reset | | _________________________________________ _______ _________ | | | | | | | | | | | | | | | | | '-->| TS| T0|TA1|TB1|TC1|TD1|TA2|TB2|TC2|TD2| ......... | T1| ... | TK|TCK| |___|___|___|___|___|___|___|___|___|___|_ _|___|_ _|__ |___| TS : Initial character TO : Format character TAi : Interface character [ codes FI,DI ] TBi : Interface character [ codes II,PI1 ] TCi : Interface character [ codes N ] TDi : Interface character [ codes Yi+1, T ] T1, ... , TK : Historical characters (max,15) TCK : Check character Figure 4 : General configuration of the Answer to Reset
    The interface characters specify physical parameters of the integrated circuit in the card and logical characteristics of the subsequent exchange protocol.
    The historical characters designate general information, for example, the card manufacturer, the chip inserted in the card, the masked ROM in the chip, the state of the life of the card. The specification of the historical characters falls outside the scope of this part of ISO/IEC7816.
    For national simplicity, T0, TAi, ... ,TCK will designate the bytes as well as the characters in which they are contained.
    Structure of TS, the initial character
    --------------------------------------
    The initial character TS provides a bit shynchronisation sequence and defines the conventions to code data bytes in all subsequent characters. These conventions refer to ISO1177.
    I/O is initially in state Z. A bit synchronisation sequence (Z)AZZA is defined for the start bit and bits ba bb bc (see figure 5).
    The last 3 bits bg bh bi shall be AAZ for checking parity.
    NOTE : This allows the interface device to determinate the etu initially used by the card. An alternate measurement of etu is a third of the delay between the first two falling edges in TS. Transmission and reception mechanisms in the card shall be consistent with the alternate
    definition of etu.
    The two possible values of TS (ten consecutive bits from start to bi and corresponding hexadecimal value) are
    - Inverse convention : (Z)ZZAAAAAZ
    where logic level ONE is A, ba is b8 (msb is first), equal to $3F when decoded by inverse convention.
    - Direct convention : (Z)ZZAZZZAAZ
    where logic level ONE is Z, ba is b1 (lsb first), equal to $3B when decoded by direct convention.
    Start ba bb bc bd be bf bg bh bi Z ____ _______ ___________ ______ | | | | | Z Z Z | | | | (Z)| A | Z Z | A | or | | Z (Z) A |___| |___|_A___A___A_|___|___| Figure 5 : Initial character TS --------Structure of the subsequent characters in the Answer to Reset
    -------------------------------------------------------------
    The initial character TS is followed by a variable number of subsequent characters in the following order: The format character T0 and, optionally the interface characters TAi, TBi, TCi, TDi and the
    historical characters T1, T2, ... , TK and conditionally, the check character TCK.
    The presence of the interface characters is indicated by a bit map technique explained below.
    The presence of the historical characters is indicated by the number of bytes as specified in the format character defined below.
    The presence of the check character TCK depends on the protocol type(s) as defined as below.
    - Format character T0
    -------------------
    The T0 character contains two parts:
    - The most significant half byte (b5, b6, b7, b is named Y1 and indicates with a logic level ONE the presence of subsequent characters TA1, TB1, TC1, TD1 respectively.
    - The least significant half byte (b4 to b1) is named K and indicates the number (0 to 15) of historical characters.
    ,----,----,----,----,----,----,----,----, | b8 | b7 | b6 | b5 | b4 | b3 | b2 | b1 | '----'----'----'----'----'----'----'----' :<------- Y1 ------>:<-------- K ------>: Y1 : indicator for the presence of the interface characters TA1 is transmitted when b5=1 TB1 is transmitted when b6=1 TC1 is transmitted when b7=1 TD1 is transmitted when b8=1 K : number of hitorical characters Figure 6 : Informations provided by T0 --------
    - Interface characters TAi, TBi, TCi, TDi
    ---------------------------------------
    TAi, TBi, TCi (i=1, 2, 3, ... ) indicate the protocol parameters.
    TDi indicates the protocol type T and the presence of subsequent
    characters.
    Bits b5, b6, b7, b8 of the byte containing Yi (T0 contains Y1; TDi contains Yi+1) state whelther character TAi for b5, character TBi for b6, character TCi for b7, character TDi for b8 are or are not (depending on whether the relevant bit is 1 or 0) transmitted subsequently in this
    order after the character containing Yi.
    When needed, the interface device shall attribute a default value to information corresponding to a non transmitted interface character.
    When TDi is not transmitted, the default value of Yi+1 is null, indicating that no further interface characters TAi+j, TBi+j, TCi+j, TDi+j will be transmitted.
    ,----,----,----,----,----,----,----,----, | b8 | b7 | b6 | b5 | b4 | b3 | b2 | b1 | '----'----'----'----'----'----'----'----' :<------ Yi+1 ----->:<------- T ------->: Yi+1 : indicator for the presence of the interface characters TAi+1 is transmitted when b5=1 TBi+1 is transmitted when b6=1 TCi+1 is transmitted when b7=1 TDi+1 is transmitted when b8=1 T : Protocol type for subsequent transmission. Figure 7 : Informations provided by TDi --------
    - Historical characters T1, T2, ... ,TK
    -------------------------------------
    When K is not null, the answer to reset is continued by transmitting K historical characters T1, T2, ... , TK.
    - Check character TCK
    -------------------
    The value of TCK shall be such that the exclusive-oring of all bytes from T0 to TCK included is null.
    The answer to reset is complete 12 etu after the leading edge of the last character.

    Protocol type T
    ---------------
    The four least significant bits of any interface character TDi indicate a protocol type T, specifying rules to be used to process transmission protocols. When TDi is not transmitted, T=0 is used.
    T=0 is the asynchronous half duplex character transmission protocol.
    T=1 is the asynchronous half duplex block transmission protocol.
    T=2 and T=3 are reserved for future full duplex operations.
    T=4 is reserved for an enhanced asynchronous half duplex character
    transmission protocol.
    T=5 to T=13 are reserved for future use.
    T=14 is reserved for protocols standardized by ISO.
    T=15 is reserved for future extension.
    NOTE : If only T=0 is indicated, TCK shall not be sent. In all other cases TCK shall be sent.
    Specifications of the global interface bytes
    --------------------------------------------
    Among the interface bytes possibly transmitted by the card in answering to reset, this subclaus defines only the global interface bytes TA1,TB1, TC1, TD1.
    These global interface bytes convey information to determine parameters which the interface device shall take into account.
    - Parameters F, D, I, P, N
    ------------------------
    This initial etu is used during answer to reset is replaced by the work etu during subsequent transmission. F is the clock rate conversion factor and D is the bit rate adjustment factor to determine the work etu in subsequent transmissions.
    For internal clock cards:
    initial etu = 1/9600 s work etu = (1/D)*(1/9600) s
    For external clock cards:
    initial etu = 372/fi s work etu = (1/D)*(F/fs) s
    The minimum value of fs shall be 1MHz.
    The maximum value of fs is given by table 6.
    I and P define the active state at VPP.
    - Maximum programming current : Ipp = 1mA
    - Programming voltage : Vpp = P.V
    N is an extra guardtime requested by the card. Before receiving the next character, the card requires a delay of at least (12+N) etu from the start leading edge of the previous character. No extra guardtme is used to send characters from the card to the interface device.
    The default values of these parameters are:
    F = 372 ; D = 1 ; I = 50 ; P = 5 ; N = 0

    - Integer values in global interface bytes
    ----------------------------------------
    The global interface bytes, TA1, TB1, TC1, TB2 code integer values FI, DI II, PI1, N, PI2 which are either equal to or used to compute the values of the parameters F, D, I, P, N presented above.
    TA1 codes FI over the most significant half byte (b8 to b5) and DI over the least significant half byte (b4 to b1).
    TB1 codes II over the bits b7 and b6, and PI1 over the 5 least significant bits b5 to b1. The most significant bit b8 equals to 0.
    NOTE : The interface device may ignore the bit b8 of TB1.
    TC1 codes N over the eight bits (b8 to b1).
    TB2 codes PI2 over the eight bits (b8 to b1).


    Table 6: Clock rate conversion factor F ------- ---------------------------------------------------------------------- FI | 0000 0001 0010 0011 0100 0101 0110 0111 --------------+------------------------------------------------------- F | Internal clk 372 558 744 1116 1488 1860 RFU --------------+------------------------------------------------------- fs (max) MHz | - 5 6 8 12 16 20 - ---------------------------------------------------------------------- --------------------------------------------------------------- FI | 1000 1001 1010 1011 1100 1101 1110 1111 --------------+------------------------------------------------ F | RFU 512 768 1024 1536 2048 RFU RFU --------------+------------------------------------------------ fs (max) MHz | - 5 7.5 10 15 20 - - --------------------------------------------------------------- RFU : Reserved for Future Use Table 7: Bit rate afjustment factor D ------- ------------------------------------------------------- DI | 0000 0001 0010 0011 0100 0101 0110 0111 ------+------------------------------------------------ D | RFU 1 2 4 8 16 RFU RFU ------------------------------------------------------- ------------------------------------------------------- DI | 1000 1001 1010 1011 1100 1101 1110 1111 ------+------------------------------------------------ D | RFU RFU 1/2 1/4 1/8 1/16 1/32 1/64 ------------------------------------------------------- RFU : Reserved for Future Use
    - Programming voltage factor P
    ---------------------------- PI1 from 5 to 25 gives the value of P in volts. PI1=0 indicates that VPP is connected in the card which generates an internal programming voltage from VCC. Other values of PI1 are reserved for future use.
    When PI2 is present, the indication of PI1 should be ignores. PI2 from 50 to 250 gives the value of P in 0.1V. Other values of PI2 are reserved for future use.
    Table 8 : Maximum programming current factor I ------- ------------------------------- II | 00 01 10 11 -----+------------------------- I | 25 50 100 RFU -------------------------------- Extra guardtime N
    -----------------
    N codes directly the extra guard time, from 0 to 254 etu. N=255 indicates that the minimum delay between the start edges of two consecutives characters is reduced to 11 etu.

    b - Answer to Reset in synchronous transmission
    -------------------------------------------
    * Clock frequency and bit rate
    """"""""""""""""""""""""""""
    There is a linear relationship between the bit rate on the I/O line and the clock frequency provided by the clock interface device on CLK.
    Any clock frequency between 7kHz and 50kHz may be chosen for the reset sequence. A clock frequency of 7kHz corresponds to 7kbit/s, and values of the clock frequency up to 50kHz cause corresponding bit rates to be transmitted.
    * Structure of the header of the Answer to Reset
    """"""""""""""""""""""""""""""""""""""""""""""
    The reset operation results in an answer from the card containing a header transmitted from the card to the interface. The header has a fixed length of 32 bits and begins with two mandatory fields of 8 bits, H1 and H2.
    The chronological order of transmission of information bits shall correcpond to bit identification b1 to b32 with the least significant bit transmitted first. The numerical meaning corresponding to each
    information bit considered in isolation is that of the digit.
    - 0 for a unit corresponding to state A (space)
    - 1 for a unit corresponding to state Z (mark)
    * Timing of the haeder
    """"""""""""""""""""
    After the reset procedure, the output information is controlled by clock pulses. The first clock pulse is applied between 10us and 100us (t14) after the falling edge on RST to read the data bits from the card. State H of the clock pulses can be varied between 10us and 50us (t15) and state L between 10us and 100us (t16).
    The first data bit is obtained on I/O while the clock is low and is valid 10us (t13) at least after the falling edge on RST. The following data bits are valid 10us (t17) at least after the falling edge on CLK. Each data bit is valid until the next falling edge the following clock pulse on CLK. The data bits can therefore be sampled at the rising edge of the following clock pulses.
    * Data content of the header
    """"""""""""""""""""""""""
    The header allows a quick determination of whelther the card and the interface device are compatible. If there is no compatibility, the contacts shall be desactivated.
    The first field H1 codes the protocol type. The values of the codes and the corresponding protocol type are
    Hexadecimal value protocol type
    -----------------------------------
    00 and ff not to be used
    01 to FE each value is assigned
    by ISO/IEC JTC1/SC17 to
    one protocol type
    The second field H2 codes parameters for the protocol type coded in field H1. The values of H2 are to be assigned by ISO/IEC JTC1/SC17.

    ISO7816 3.4 Protocol type selection (PTS)

    If only one protocol type and FI=D=1 (default value of TA1) and N smaller than 255 is indicated in the answer to reset. The transmission protocol associated to the protocol type may be started immediately after the transmission of answer to reset.
    If more than one protocol type and/or TA1 parameter values other than the default values and/or N equeal to 255 is/are indicated in the answer to reset, the card shall know unambiguously, after having sent the answer to reset, which protocol type or/and transmission parameter values (FI, D, N) will be used. Consequently a selection of the protocol type and/or the transmission parameters values shall be specified.
    If the card is able to process more than one protocol type and if one of those protocol types is indicated as T=0, then the protocol type T=0 shall indicated in TD1 as the first offered protocol, and is assumed if no PTS is performed.
    If a card offers more than one protocol and if the interface device supports only one of these protocols which is not T=0 and does not support PTS, the interface should reject or reset the card.

 

 

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